Design Of Cascaded Analog-To-Digital Converter By Using Voltage Controlled Oscillator

In this paper, we present analysis on the operation and architecture of the voltage controlled oscillator (VCO)based ADC is presented. The VCO-based quantizer is analyzed for two different architectures, one using a frequency-todigital converter (FDC) the other a time-to-digital converter (TDC). The advantages of quantizing the first-stage residue in time domain versus with a voltage domain are presented. The requirement of gain for an opamp for the first-stage residue amplifier is relaxed by using reference-scaling and reference recycling schemes which enables the use of a very simple telescopic cascode amplifier in the gain stage. The second-stage VCO linearity is improved by a differential measurement of VCO frequency. Power consumption in the second stage is reduced by using time-to-digital conversion for fine quantization of the VCO phase. Simulation results are presented for the design of a 13-bit 20-Msps ADC in 65-nm CMOS process. The estimated power dissipation of this converter is less than 1 mW. Keywords—Analog-to-digitalconverter(ADC), calibration,time-to-digital converter (TDC), two-step ADC, voltagecontrolledoscillators (VCOs).